Data processing devices frequently employ multiple clock signals to synchronize the operations of the device. In order to reduce the impact of signal propagation delays, clock skew, and other clock signal perturbations on device performance, it is sometimes desirable to adjust the phase of one or more of the device clock signals relative to a reference clock signal. One phase adjustment technique includes the use of a programmable delay module (PDM) such as a phase locked loop (PLL) and a delay locked loop (DLL). Because phase adjustment of clock signals can have an impact on device performance, it is typically desirable to test each PDM to ensure its performance matches a specification. However, because PDMs typically include analog circuitry and do not operate in a purely synchronous manner, testing of these devices can be difficult and require considerable device area be dedicated to test-related circuitry.
The use of the same reference symbols in different drawings indicates similar or identical items.